`define SIMULATION
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// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
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// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
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module scm_aux
(

    input       iClk,
    input       iRst_n,

    input       iAUX_SEQ_EN,
    input       iPWRGD_P1V05_SCM_AUX,       // From P1V05 SCM AUX VR, since this is the last stage SCM card VR, so can indicate all SCM card VRs are fully on
    input       iPWRGD_P1V0_BMC_AUX,        // From P1V0 BMC AUX VR, since this is the last stage runBMC card VR, so can indicate all runBMC card VRs are fully on
    input       iRST_DEDI_BUSY_CPU0_N,
    input       iRST_DEDI_BUSY_CPU1_N,
    input       iRST_BMC_SRST_DIO_N,
    input       iFM_HPM_STBY_RDY,           // From main FPGA logic, indicate legacy processor VCCFA_EHV and VNN power rails are fully on
    input       iCPU1_AUX_PWR_OK,           // From main FPGA through LTPI, indicate CPU1 AUX power rails are fully on

    output reg  oBMC_VR_EN,                 // To runBMC card first stage VR, enable all runBMC card VRs stage by stage
    output reg  oSCM_BMC_AUX_PWR_OK,        // To main FPGA, indicate all VRs on SCM card and runBMC card are fully on (Not used now)
    output reg  oSCM_BMC_AUX_PWR_FAULT,     // To main FPGA logic through LTPI, indicate SCM card or runBMC card VR failure
    output reg  oSCM_PWR_FAULT,             // To debug FPGA through LTPI and sGPIO, indicate SCM card VR failure for postcode display
    output reg  oBMC_PWR_FAULT,             // To debug FPGA through LTPI and sGPIO, indicate runBMC card VR failure for postcode display
    output      oRST_SRST_BMC_N,            // To PFR, indicate all VRs on SCM card and runBMC card are fully on, can release BMC SRST#
    output      oPWRGD_AUX_PWRGD_CPU0,      // To PFR, indicate legacy processor VCCFA_EHV and VNN power rails are fully on, can release CPU_AUX_PWRGD
    output      oPWRGD_AUX_PWRGD_CPU1       // To PFR, CPU1 VCCFA_EHV and VNN power rails are fully on, can release CPU1 AUX_PWRGD

);

/*************************************************************************************************************
 * Local Parameter Definitions                                                                               *
 *************************************************************************************************************/
    localparam  LOW  = 1'b0;
    localparam  HIGH = 1'b1;
    
    `ifdef SIMULATION
        localparam  T_2mS_2M   =  12'd4;
        localparam  T_50mS_2M  =  17'd10;
    `else 
        localparam  T_2mS_2M   =  12'd4000;
        localparam  T_50mS_2M  =  17'd100000;
    `endif

/*************************************************************************************************************
 * Local Registers and Wires Definitions                                                                     *
 *************************************************************************************************************/
    reg         rPWRGD_P1V05_SCM_AUX_FF1;
    reg         rPWRGD_P1V0_BMC_AUX_FF1;
    reg         rSCM_PWR_FAULT_FF1;
    reg         rBMC_PWR_FAULT_FF1;

    wire        wPWRGD_All_VRs_DLY_2mS;
    wire        wRST_SRST_BMC_DLY_50mS;

/*************************************************************************************************************
 * Logic                                                                                                     *
 *************************************************************************************************************/
    assign oRST_SRST_BMC_N       = wPWRGD_All_VRs_DLY_2mS ? oSCM_BMC_AUX_PWR_OK : LOW;  // Indicate all VRs on SCM card and runBMC card are fully on, can release BMC SRST# now
    assign oPWRGD_AUX_PWRGD_CPU0 = wRST_SRST_BMC_DLY_50mS ? iFM_HPM_STBY_RDY : LOW;     // Indicate legacy processor VCCFA_EHV and VNN power rails are fully on and delay done, can release CPU_AUX_PWRGD
    assign oPWRGD_AUX_PWRGD_CPU1 = wRST_SRST_BMC_DLY_50mS ? iCPU1_AUX_PWR_OK : LOW;     // Indicate CPU1 VCCFA_EHV and VNN power rails are fully on and delay done, can release CPU1 AUX_PWRGD now

    always @ ( posedge iClk or negedge iRst_n) begin
        if(!iRst_n) begin
            oBMC_VR_EN                  <= LOW;
            rPWRGD_P1V05_SCM_AUX_FF1    <= LOW;
            rPWRGD_P1V0_BMC_AUX_FF1     <= LOW;
            rSCM_PWR_FAULT_FF1          <= LOW;
            rBMC_PWR_FAULT_FF1          <= LOW;
            oSCM_PWR_FAULT              <= LOW;
            oBMC_PWR_FAULT              <= LOW;
            oSCM_BMC_AUX_PWR_FAULT      <= LOW;
            oSCM_BMC_AUX_PWR_OK         <= LOW;
        end
        else begin
            oBMC_VR_EN                  <= iAUX_SEQ_EN;
            rPWRGD_P1V05_SCM_AUX_FF1    <= iPWRGD_P1V05_SCM_AUX;
            rPWRGD_P1V0_BMC_AUX_FF1     <= iPWRGD_P1V0_BMC_AUX;
            rSCM_PWR_FAULT_FF1          <= (rPWRGD_P1V05_SCM_AUX_FF1 && !iPWRGD_P1V05_SCM_AUX) ? HIGH : rSCM_PWR_FAULT_FF1;
            rBMC_PWR_FAULT_FF1          <= (rPWRGD_P1V0_BMC_AUX_FF1  && !iPWRGD_P1V0_BMC_AUX ) ? HIGH : rBMC_PWR_FAULT_FF1;
            oSCM_PWR_FAULT              <= rSCM_PWR_FAULT_FF1;
            oBMC_PWR_FAULT              <= rBMC_PWR_FAULT_FF1;
            oSCM_BMC_AUX_PWR_FAULT      <= (rSCM_PWR_FAULT_FF1 || rBMC_PWR_FAULT_FF1) ? HIGH : oSCM_BMC_AUX_PWR_FAULT;
            oSCM_BMC_AUX_PWR_OK         <= (rPWRGD_P1V05_SCM_AUX_FF1 && rPWRGD_P1V0_BMC_AUX_FF1);         
        end
    end

/*************************************************************************************************************
 * Instances                                                                                                 *
 *************************************************************************************************************/
// TC: min 50 ms delay for release SRST#
    delay #(.COUNT(T_50mS_2M)) PWR_OK_50mS_DLY
        (
            .iClk    (iClk                   ),
            .iRst    (iRst_n                 ),
            .iStart  (oRST_SRST_BMC_N        ),
            .iClrCnt (1'b0                   ),
            .oDone   (wRST_SRST_BMC_DLY_50mS )
        );

// T: min 2 ms delay for release SRST#
    delay #(.COUNT(T_2mS_2M)) PWR_OK_2mS_DLY
        (
            .iClk    (iClk                   ),
            .iRst    (iRst_n                 ),
            .iStart  (oSCM_BMC_AUX_PWR_OK    ),
            .iClrCnt (1'b0                   ),
            .oDone   (wPWRGD_All_VRs_DLY_2mS )
        );

endmodule
